
--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   16:58:54 04/25/2012
-- Design Name:   ControlUnit
-- Module Name:   C:/procesador/ControlUnit/ControlUnit/ControlUnit_Suma_tb.vhd
-- Project Name:  ControlUnit
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: ControlUnit
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
USE work.definitions.ALL;

ENTITY ControlUnit_Suma_tb_vhd IS
END ControlUnit_Suma_tb_vhd;

ARCHITECTURE behavior OF ControlUnit_Suma_tb_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT ControlUnit
	PORT(
		clr : IN std_logic;
		clk : IN std_logic;
		inst_ack_in : IN std_logic;
		data_ack_in : IN std_logic;
		port_ack_in : IN std_logic;
		interrupt : IN std_logic;
		IR : IN std_logic_vector(17 downto 0);          
		is_load : OUT std_logic;
		is_store : OUT std_logic;
		is_in : OUT std_logic;
		is_out : OUT std_logic;
		is_branch : OUT std_logic;
		is_reti : OUT std_logic;
		is_sub_ret : OUT std_logic;
		is_jump : OUT std_logic;
		is_call : OUT std_logic;
		is_immediate : OUT std_logic;
		is_shift : OUT std_logic;
		is_interrupt : OUT std_logic;
		is_rw : OUT std_logic;
		pc_reset : OUT std_logic;
		loadEnable_IR : OUT std_logic;
		enable_acc : OUT std_logic;
		enable_data : OUT std_logic;
		enableStack : OUT std_logic;
		enable_flags : OUT std_logic;
		ena_mem_port_data : OUT std_logic;
		opType : OUT std_logic_vector(2 downto 0);
		branchOp : OUT std_logic_vector(1 downto 0);
		uc_status : OUT state_type
		);
	END COMPONENT;

	--Inputs
	SIGNAL clr :  std_logic := '0';
	SIGNAL clk :  std_logic := '0';
	SIGNAL inst_ack_in :  std_logic := '0';
	SIGNAL data_ack_in :  std_logic := '0';
	SIGNAL port_ack_in :  std_logic := '0';
	SIGNAL interrupt :  std_logic := '0';
	SIGNAL IR :  std_logic_vector(17 downto 0) := (others=>'0');

	--Outputs
	SIGNAL is_load :  std_logic;
	SIGNAL is_store :  std_logic;
	SIGNAL is_in :  std_logic;
	SIGNAL is_out :  std_logic;
	SIGNAL is_branch :  std_logic;
	SIGNAL is_reti :  std_logic;
	SIGNAL is_sub_ret :  std_logic;
	SIGNAL is_jump :  std_logic;
	SIGNAL is_call :  std_logic;
	SIGNAL is_immediate :  std_logic;
	SIGNAL is_shift :  std_logic;
	SIGNAL is_interrupt :  std_logic;
	SIGNAL is_rw :  std_logic;
	SIGNAL pc_reset :  std_logic;
	SIGNAL loadEnable_IR :  std_logic;
	SIGNAL enable_acc :  std_logic;
	SIGNAL enable_data :  std_logic;
	SIGNAL enableStack :  std_logic;
	SIGNAL enable_flags :  std_logic;
	SIGNAL ena_mem_port_data :  std_logic;
	SIGNAL opType :  std_logic_vector(2 downto 0);
	SIGNAL branchOp :  std_logic_vector(1 downto 0);
	SIGNAL uc_status :  state_type;

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: ControlUnit PORT MAP(
		clr => clr,
		clk => clk,
		inst_ack_in => inst_ack_in,
		data_ack_in => data_ack_in,
		port_ack_in => port_ack_in,
		is_load => is_load,
		is_store => is_store,
		is_in => is_in,
		is_out => is_out,
		is_branch => is_branch,
		is_reti => is_reti,
		is_sub_ret => is_sub_ret,
		is_jump => is_jump,
		is_call => is_call,
		is_immediate => is_immediate,
		is_shift => is_shift,
		is_interrupt => is_interrupt,
		is_rw => is_rw,
		interrupt => interrupt,
		pc_reset => pc_reset,
		loadEnable_IR => loadEnable_IR,
		enable_acc => enable_acc,
		enable_data => enable_data,
		enableStack => enableStack,
		enable_flags => enable_flags,
		ena_mem_port_data => ena_mem_port_data,
		opType => opType,
		branchOp => branchOp,
		IR => IR,
		uc_status => uc_status
	);

	tb : PROCESS
	BEGIN
		
			clr <= '1';
			
		wait for 100 ns;
			
			clr <= '0';
			inst_ack_in <= '1';
			
			IR <= "111011111111100000";  -- suma
		
			wait; -- will wait forever
	END PROCESS;
	
	clk_process: PROCESS
	BEGIN
	
		clk <= '0';
		wait for 50 ns;
		clk <= '1';
		wait for 50 ns;
	
	END PROCESS;

END;
